E4 Computer Engineering builds on 20+ years of developing and integrating innovative technologies and announces Monte Cimone, a cluster aimed at enabling on RISC-V ISA the co-design of high performance scientific and engineering applications and the supporting software stack. Monte Cimone is currently undergoing the final validation tests at DEI-UNIBO and a similar architecture, albeit at a smaller scale, is located at E4’s R&D lab for further developments. These systems are available to the members of the OEHI for enabling the porting of applications against the RISC-V ISA, code testing, code development and Proof-of-Concept.
Monte Cimone is the first RISC-V ISA cluster specifically designed, built, and validated for co-design activities targeted to enable its use in the HPC ecosystem and having an operational environment as the primary target. Monte Cimone enables developers to test and validate scientific and engineering workloads in a rich software stack, including development tools, libraries for message-passing programming, BLAS, FFT, drivers for HS networks and I/O devices. The objective is to achieve a future-ready position capable of addressing and leveraging the features of the RISC-V ISA for scientific and engineering applications and workloads in an operational environment.
The key hardware components of Monte Cimone are:
- 6 dual-board servers, with a form factor of 4.44 cm (1 Rack Unit) high, 42.5 cm width, 40 cm deep. Each board follows the Industry Standard Mini-ITX form factor (170 mm per 170 mm);
- Each board features one SiFive Freedom U740 SoC, 16 GB of 64-bit DDR memory operating at 1866s MT/s and high-speed interconnects with PCIe Gen 3 x8 operating at 7.8 GB/s, one Gigabit Ethernet, and four USB 3.2 Gen 1;
- In RV007 system the M.2 M-key expansion slot is occupied by a 1 TB NVME2280 SSD Module storage device used by the Operating System. The Micro SD card is present and used for the UEFI Boot;
- Two 250 W power supplies are integrated inside the case to support the current hardware and future PCIe accelerators and expansion boards;
- Integrated fans
RISC-V is a very promising ISA for HPC. The European Processor Initiative will use a RISC-V based accelerator. An intense development effort is taking place these days to gauge the maturity of the current generation of RISC-V based processors with the most intense HPC workload. Prof. Luca Benini (DEI-UNIBO), a key member of the EPI consortium and a driving force behind the development of RISC-V, proposed E4 and CINECA to begin a development process that would eventually become Monte Cimone.
Monte Cimone will be used as a platform for porting and tuning HPC-relevant software stacks and HPC applications to the RISC-V architecture. The hardware will be further extended by adding PCEe acceleration cards to explore heterogeneous architectures and based on RISC-V. Complementing the rich set of HW components, the porting of the Infiniband stack is ongoing and will be added to the current configuration as soon as validated. The modularity of the cluster architecture will enable its extensions with new blades hosting higher performance RISC-V processors, memories and storage components as they will become available on the market.
Media Contact for E4 Computer Engineering