Arm and RISC-V: Competition versus Synergies Workshop

This workshop brings together experts in ARM and RISC-V computing to share current practices in HPC hard- and software design and also discuss competition and synergies.

Date and time
Tue, June 22, 2021
4:00 PM – 6:00 PM CEST

Register here

About this event

ARM is the most successful microprocessor architecture on the planet, with its licensees shipping billions of chips a year. Emerging in 2010 from the Parallel Computing Lab at UC Berkeley in California, RISC-V is a modular architecture that allows developers to build whatever they desire on top of the core instruction set. For both Instruction Set Architectures significant efforts are being made to establish them in the area of high-performance computing.

ARM is based on proprietary IP, and the companies license their products. RISC-V is a royalty-free specification architecture that is growing in popularity with developers around the world. Open-source RISC-V based cores are available, and there are also commercially licensed cores, bringing risk of IP fragmentation. ARM has an extremely large online community, support structure, and libraries to help designers target many different platforms including microcontrollers, microprocessors, and servers. As RISC-V is a relatively new instruction set, it’s still growing in terms of support for software and programming environments.

This workshop brings together representatives from large data centers, system integrators, end-users, microprocessor designers and experts who lead efforts in developing solutions on ARM and RISC-V for today’s platforms and upcoming Exascale systems. The objective is to share current practices for both ARM and RISC-V hardware and software stacks, and to discuss how and where ARM and RISC-V can be competitors and where they can be synergistic.

PROGRAM

Time	Duration	Title	Speaker
4:00 PM	5 mins	Open Edge and HPC Initiative (OEHI) Introduction	Fabrizio Magugliani Strategic Planning and Business Development E4 COMPUTER ENGINEERING
4:05 PM	5 mins	Huawei in OEHI The talk will give insights into how partners are using the OEHI infrastructure and how it helps to improve scientific computing and optimise middleware service for new computer architecture like ARMv8	Heiko Joerg Schick Chief Architect, Advanced Computing Huawei Technologies Munich
4:10 PM	10 mins	ARM technologies for HPC Update on the latest announcements and activities	Dr. Fabrice Dupros ARM
4:20 PM	10 mins	HPC Opportunities: Past, Present, and in the Future Historically, research has been stifled by the lack of open platforms leading to computer architecture simulation and questionable results. This has led to slow adoption of some research ideas. With the slowing of Moore’s law, specialization and software/hardware co-design are critical requirements to meet the goals of future HPC systems. In this talk, I will present a few of the past, present and future in HPC and how Arm and RISC-V are playing different roles.	Dr. John Davis Group Manager – European Exascale Accelerator Barcelona Supercomputing Center
4:30 PM	10 mins	European Processor Initiative: the place where ARM and RISC-V live in peace The European Processor Initiative (EPI) has been set to address the EU need for sovereignty in HPC compute engines. EPI develops technologies at high TRL, for short term needs, based on ARM ISA, and develop technologies at low TRL, for long term needs, based on RISC-V ISA. In this presentation, it will be discussed how EPI combines both objectives on the same platform.	Jean-Marc Denis Atos Chief of Staff , BDS Strategy & Innovation Distinguished Expert Chair of the Board European Processor Initiative
4:40 PM	10 mins	A Tale of Vectors While commercially rivals, Arm and RISC-V can benefit from synergies in the open source space. In this talk I will try to make my point with an example of the work carried out in LLVM in order to support Arm SVE and RISC-V.	Roger Ferrer Ibáñez Senior Research Engineer Compilers and Toolchains for HPC Barcelona Supercomputing Center
4:50 PM	10 mins	Coffee break
5:00 PM	40 mins	Panel Discussion on “Arm and RISC-V: Competition versus Synergies”	Moderator: Prof. Dirk Pleiter Panel: Dr. Daniele Cesarini (CINECA), Jean-Marc Denis (Atos, EPI), Roger Ferrer Ibáñez (BSC) , Fabrizio Magugliani (E4)
5:40 PM	20 mins	Audience Q&A

UPDATE 2021-06-23: Added the slides of the talks.